In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and power consumption. As the size of the individual circuit elements is reduced, so is the available real estate for conductive interconnects in integrated circuits. Consequently, these interconnects have to be reduced to compensate for a reduced amount of available real estate and for an increased number of circuit elements provided per chip.
In integrated circuits having minimum dimensions of approximately 0.35 μm and less, a limiting factor of device performance is the signal propagation delay caused by the switching speed of the transistor elements. As the channel length of these transistor elements has now reached 0.18 μm and less, however, capacitance between neighboring conductive structures is increasingly problematic. Parasitic RC time constants therefore require the introduction of a new materials and methods for forming metallization layers.
Traditionally, metallization layers are formed by a dielectric layer stack, including, for example, silicon dioxide and/or silicon nitride with aluminum as the typical metal. Since aluminum exhibits significant electromigration at higher current densities, copper is replacing aluminum. Copper has significantly lower electrical resistance and reduced electromigration problems.
The introduction of copper, however, entails a plurality of issues to be dealt with. For example, copper may not be efficiently patterned by well-established anisotropic etch processes and therefore the so-called damascene technique is employed in forming metallization layers including copper lines. A further issue is the ability of copper to readily diffuse in silicon dioxide. Therefore, copper diffusion may negatively affect device performance, or may even lead to a complete failure of the device. It is therefore necessary to provide a diffusion barrier layer between the copper surfaces and the neighboring materials to substantially prevent copper from migrating to sensitive device regions. Silicon nitride (SiN), titanium nitride (TiN), and tantalum nitride (TaN) are known as effective copper diffusion barriers and are thus frequently used as dielectric barrier materials separating a copper surface from an interlayer dielectric, such as silicon dioxide. These barrier layer materials are typically deposited using current deposition techniques, such as physical vapor deposition (PVD) and atomic layer deposition (ALD). However, these deposition techniques for application of pattern material do not provide uniformity in pattern shape owing to a faster rate of deposition of the barrier layer material at an upper portion of the pattern as opposed to a lower portion of the pattern, thereby causing non-uniformity. Additionally, PVD and ALD require high temperatures and are costly.